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Complete list of collected requirements for the Analog extention to VHDL. Mart Altmae/Kevin Nolan The purpose of this document is to summarize all requirements submitted to the sub-par 1076.1 for analog extentions to VHDL. It includes the ones relating to analog matters, which were already submitted to the VHDL'92 restandardization effort, as presented by Kevin Nolan in his document on consolidated North American and European Analog VHDL Requirements, the additional ones collected by Mart Altmae, and finally a few new North American requirements, presented by Kevin Nolan at the VHDL-Forum meeting in Santander last April. VHDL'92 requirements, collected by Kevin Nolan: ============================================== 1. Support for Continuous Time Generated by: NA1, E48 Summary: The execution of a VHDL model must be extended from the notion of the evaluation of events at discrete points in time to the notion of continuous evaluation over continuous time. 2. Mixed mode support: conversion between analog and digital domains Generated by: NA2, E48 Summary: Objects defined using discrete time semantics (signals) and continuous time semantics (waveforms) must be able to com- municate with one another to provide the ability to perform mixed-mode simulation. 3. Support for analog pins and a way to connect them Generated by: NA3, E13, E16 Summary: Electrical circuits are typically described as an interconnection of elements that exhibit some electrical behavior. The connection points at the elements are defined in terms of ports. Each electrical port consists of two physical connection points that are defined as terminals (N-Port Theory). 4. Analog pin behavior conforming to conservation laws Generated by: NA4, E16 Summary: The objective is to describe the physical operation of circuits. The most common method is the use of Kirchoffs current and voltage laws. We therefore speak of electrical behavior in terms of currents flowing through the branches and the voltages across nodes of a network 5. New operators and intrinsics to support domain conversion and the specification of derivatives Generated by: NA5 Summary: To support the conversion from analog domain to digital domain a threshold function is needed in order to schedule events on the digital side. Conversely, a analog waveform generator function is needed to support the conversion of digital signals to analog waveforms. In order to model certain analog devices, a time-derivative operator is required. 6. Specification of error tolerances to be used by numerical algorithms used to solve the analog system Generated by: NA6, E16 Summary: Since analog simulation employs numerical methods in order to solve a system of ordinary differential equations, an error tolerance must be specified to bound the numerical errors generated by these methods. 7. New data types and associated operators Generated by: NA7 Summary: Several new data types are required to model various systems. Complex numbers and/or phasors (polar coordinates) are needed to model filter networks, etc. Similarly, transcendental functions are required to model semiconductors. 8. Specification of generics whose value can be dependent on time or other system variables Generated by: E13, E16 Summary: It is necessary for modeling non-linear devices (e.g. semiconductors) to define models having the value of certain parame- ters vary as a function of time or the state of other simulation variables. 9. Definition of new pin types and semantics to be specified by users Generated by: E16, E24, E48 Summary: To model systems containing non-electrical or hybrid devices, it must be possible to define custom pin types. For example, rotational pins would be used to model motors, thermal pins to describe self-heating electrical systems, etc. The conserved properties of these custom pin types most also be specified. 10. Ability to reference the through, (e.g. current) and across (e.g. voltage) components of analog entities Generated by: NA5, E16 Summary: In conserved systems, behavior is described by specifying the relationship between dependent variables of the system to the independent variables. In electrical systems, onemight specify how the current through a device is a related to the voltage across its terminals. This requires access to the current through terminals and the voltage across them. 11. Ability to specify the conservation laws associated with a user defined pin type Generated by: E16 Summary: For every type of pin that can be connected to other pins in a network, the properties of that pin which must be conserved has to be supplied. In electrical systems, the usual conservation laws are given by KCL, and KCL. Analogous conservation laws must be specified for non-electrical systems. 12. Specification of error tolerances for a specific node Generated by: E16 Summary: It is desireable to be able to specify the maximum relative error when using KCL to calculate the current through a spe- cific node. According to KCL the current through any node will always sum to zero. The maximum relative error at that node would be the ratio of the difference between the currents flowing into the node to the currents flowing out. 13. Specification of and event trigger threshold to cause evaluation of a event driven process body Generated by: E16 Summary: In order to determine whether an digital event has occurred as a result of an analog state change, it is desirable to allow the specification of the minimum analog change threshold to con- trol the evaluation of a process body. A higher value for this parameter would cause fewer evaluations of the process body and therefore faster simulation, a lower value would result in more evaluations, longer simulations, and possibly greater simulation accuracy at the analog transition points. 14. Allow specification of a foreign simulator interface Generated by: E24, E46 Summary: To allow VHDL to communicate with foreign (non-VHDL) simulators, it is required to allow the specification of a foreign simulator interface. 15. Inclusion of DC operating point analysis as part of time-zero initialization and a way to conditionaly execute blocks based upon the initialization state. Generated by: E47 Summary: Electrical systems have what is called a dc operating point. This describes the quiescent state of the system at time-zero. Usually, before the simulation of a transient behavior, the dc operating point must be computed. To accommodate this, the initialization semantics of VHDL must be extended to include dc analysis. It is also necessary to control the execution of behavior blocks based upon the initialization state. In other words, it must be possible to only execute certain blocks at the dc operating point and at no other time. The following requirements were also submitted to VHDL'92. ========================================================= 16. Analog Modeling Generated by: A17 Summary: To allow the description of analog system/circuit behavior from the following perspectives: discrete-event models of digital circuits, continous-time descriptions of analog circuits, frequency-domain descriptions of analog circuits and wave-domain descriptions of microwave circuits. 17. Physical quantities Generated by: A18, E62 Summary: Support for dimensional analysis of physical quantities. 18. Introduction of simultaneous equations Generated by: E12, E63 19. Access to current value crossing an electrical component Generated by: E64 New Requirements, collected by Mart Altmae ========================================== 20. At least two labels Provisional number : E65 Summary : Description of requirement : Concerning whether or not any given simulator is conformant with IEEE-1076,it is desirable to have at least two different labels : - one for purely digital circuits : "VHDL-1076-92" ; - one for mixed, analog-digital, circuits : "AHDL-1076.1-93" ; - and possibly one for purely analog circuits, depending on how 1076.1 is specified. Also it is desirable to have a clear (static) criterion to identify a circuit (configuration, or entity plus architecture) as being digital, analog, or mixed. VHDL 92 solution : Suggested strategy : Consistent with : Different from : Opposed to : 21. Re-use digital constructs Provisional number : E66 Summary : Description of requirement : Whenever an analog (or mixed) model uses the same kind of construct as a digital one, it is desirable to use exactly the same syntax and semantics as already defined in IEEE-1076-92, to avoid misunderstandings. Examples of constructs which can be shared by digital and analog : - type definition, function definition, sequential procedure definition, - function or procedure call, ... ... Examples of constructs which are different in syntax and in semantics : - connection of several ports to a signal versus connection of several pins to a node ; - relation (or analog procedural model) versus digital process. VHDL 92 solution : Suggested strategy : Consistent with : E12, E13, E14, E16. Different from : Opposed to : 22. Definition of analog time Provisional number : E67 Summary : Description of requirement : Obviously, to perform mixed (analog-digital) descriptions and simulations, clear definitions are needed for the digital time (this already exists) and for the analog time (to be defined). Moreover the definition of the analog time should not be completely opposed to that of the digital time, to allow conversion and synchronisation. VHDL 92 solution : Suggested strategy : Digital time is defined in a very precise way by the LRM. In any given simulation, digital time may be viewed as the list of dates (each one expressed as an integer number of femto-seconds) at which at least one event occurred. Between two successive dates, nothing happens and signals keep their last value. Analog time could be defined in a similar way : it is the list of dates at which the simulator decided to compute new values for (some of) the voltages and currents. Between two successive dates, currents and voltages are, strictly speaking, unknown, but can be evaluated by interpolation. Whether each of the dates in the list is expressed by a real number (in seconds) or by an integer number (in femto- seconds) is not crucial : in fact most existing simulators could input and output dates using a VHDL-like format (integer number of femto-seconds) even if real numbers are used internally. Following this line, the opposition between "discrete" time and "continuous" time disappears. VHDL 92 solution : Suggested strategy : Consistent with : Different from : NA1 Opposed to : 23. Time synchronisation Provisional number : E68 Summary : Description of requirement : Obviously, to perform mixed (analog-digital) descriptions and simulations, clear definitions are needed for the conversion between analog and digital times. This problem is often cited and sometimes viewed as a simple problem of "type conversion" : converting a digital date (an integer number of Femto-seconds) to and from an analog date (viewed as some kind of real number, possibly in seconds). See for example "Functionnal modelling of analog blocks in VHDL ; Bernt Arbegard ; Euro-Vhdl-91, Stockholm". This conversion is necessary but not sufficient ; a definition of how digital dates and analog dates will be intermixed along the (unique) time axis is also needed. This is the problem of time synchronisation, which requires that at least a broad model of a complete mixed simulator be described : digital kernel (conformant with 1076-92, plus "hooks"), analog kernel (to be defined) and interactions between analog and digital (also to be defined). VHDL 92 solution : Suggested strategy : Assume a definition of analog time such as the one proposed in a companion requirement (provisional number rqr-ana-4 ) ; use a template of the mixed simulator (see next page) ; define a general strategy for running and suspending the analog and digital parts ; this is linked to the definition of "hooks" in the digital part (see next page) ; address the problem of fine synchronisation (see for example "Mixed VHDL - Analog Simulation, Mart Altmae, Euro-Vhdl-91, Stockholm"). Proposed sketch of the mixed simulator : ------------- -------------- | Processes | | Relations | ------------- -------------- ------ ------- | DK | <--> GK <--> | AK | ------ ------- ------------- -------------- | Signals | | ".U",".I" | ------------- -------------- On the left-hand side is the digital part, compliant with VHDL-92. It is composed of processes, signals, and the digital kernel (or DK for short). It knows the list of "analogue relevant signals" : those signals which are used, in one way or another, in the analogue part (see companion requirement rqr-ana-8). On the right-hand side is the electrical part. It is composed of differential equations, nodes and pins, and an electrical kernel (or AK for short). It knows the list of "digital relevant voltages (or currents)" : those voltages (or currents) which are used, in one way or another, in the digital part (see companion requirement rqr-ana-9). The general kernel (GK) is in charge of synchronisation between the analog part and the digital part. It is desirable to introduce as few new features as possible in the DK, and to place as few assumptions as possible on the AK. Step 1 : the DK performs normally, for some date t1, as specified in IEE1076-87; when it reaches the step where "time may advance", instead of advancing time (to t2), it suspends and reports to the GK with the following information : list of (new) values of analogue relevant signals, date of next digital event (here t2) ; Step 2 : the GK forwards this information to the AK, and starts it ; the AK should not go beyond t2 ; it may suspend before t2 (let us say at time t3) if some of the digital relevant voltage has crossed one of its relevant threshold ; the AK then suspends and reports to the GK with the following information : list of (new) values of digital relevent voltages, list of those voltages which have crossed a threshold, present date (t2 or possibly t3). step 3 : the GK forwards this information to the DK and starts it ; we can go back to step 1. New features in the DK : when it reaches the situation where "time may adavance", the DK must be capable of being suspended and restarted, possibly at some earlier date with "unforeseen" events triggered by the analogue part. Assumptions on the AK : it must be capable of calling user-supplied thresholding functions on the digital relevant voltages and of adjusting its time-step to halt before t2. Dissymmetry of the interaction : this sketch is not symmetrical : the DK may be re-started "earlier than foreseen" (at t3) while the AK is only instructed "not to go beyond t2" ; the reason is that digital signals do not change between events, while analogue voltages must be viewed as continuous. NOTE : what to do at time 0 is also to be defined. See for example requirement E47. Consistent with : NA2, E47 24. Portability of analog models Provisional number : E69 Summary : Description of requirement : In the digital domain, the semantics is defined in such a way that models are portable : the same simulation leads to the same events happening at the same dates, whichever simulator is used. Portability is also desirable for analog (and mixed) models, but must be defined in a different way, to account for the fact that solving a set of differential equations is not an exact science ! VHDL 92 solution : Suggested strategy : Define a "precision" and state that two analog simulations are equivalent if the values of any voltage or current at any date (whether actually computed or interpolated) are the same (within that precision) ; Normalize the way the equation-set is built : Starting from the structural and functionnal description of the different parts of the circuit, a single equation set will be built (at compilation or elaboration time) and solved (at simulation time) ; the contents of this equation set must be normalised. Specify the computation accuracy used for solving the equation set ; Normalize the interactions between the digital and analog parts ; Leave the rest to the implementation (detailed method used for solving the equation set, time-step management, ...). (Define a "validation suite" ?) Consistent with : NA1 Different from : Opposed to : 25. Use of existing methods Provisional number : E70 Summary : Description of requirement : The structural constructs (pins and nodes, or others) and the functionnal constructs (relations, or others) used in analog models, and the implied semantics (KCL, equations, others, ...), must be such that the building and solving of the set of differential equations may be performed using existing, proven methods. VHDL 92 solution : Suggested strategy : Review existing methods, as implemented in existing simulators ; choose a minimum set of features to be specified and normalised. Possible items : - modified nodal method for building the equation set ; - procedural models providing the branch current as a function of voltages ; - implicit states (one more equation) when the analytical solution is unknown ; - access to "old" value of a variable, and to the corresponding time-step ; - use of time derivative ; - others ... Consistent with : NA4 Different from : (E12 ?) Opposed to : 26. User control over Digital to Analog interactions Provisional number : E71 Summary : Description of requirement : Interactions from the digital part to the analog part should be user-definable ; this will allow technology-specific or application-specific interactions to be modelled at the desired level of abstraction ; it will not prevent from using "standard" packages for standard cases. VHDL 92 solution : Suggested strategy : As soon as the principles of analog functionnal modeling are defined ("relations", or procedural models) it will be easy to specify how the (up-dated) values of signals may be used inside analog models ; possible interactions : - the value of an enumerated-type (digital) signal may be used within an "if" or "case" statement to choose between several forms of a differential equation ; - the value of a real or integer signal may be used as a parameter within a differential equation ; - both may be used in the (sequential) computations taking place within a procedural model (if such a modeling technique is used). The problem of discontinuity must be addressed (i.e. a controlled voltage source which suddenly swtiches from 0V to 5V may disturb the analogue simulator). Consistent with : NA5, E48 Different from : Opposed to : 27. User control over Analog to Digital interactions Provisional number : E72 Summary : Description of requirement : Interactions from the analog part to the digital part should be user-definable ; this will allow technology-specific or application-specific interactions to be modelled at the desired level of abstraction ; it will not prevent from using "standard" packages for standard cases. VHDL 92 solution : Suggested strategy : The values of any node voltage or any pin current should be usable in the right-hand side of signal (or variable) assignement statements in the digital part ; they should also be usable in boolean expressions. The digital processes (or equivalent processes) which make use of such current or voltage values will have to be triggered when the digital conditions are met (e.g. event on a signal in the sensitivity list), and in addition they will have to be triggered also when a "significant" change occurs on one of the current or voltage they use. To avoid a great number of unnecessary calls to these processes, some form of thresholding, with user-provided functions, should be included in the analog kernel. The problem of "time-step adjustment" must be addressed (see for example "Mixed VHDL-Analog Simulation, Mart Altmae, Euro-Vhdl-91, Stockholm"). Consistent with : NA5, E48 Different from : Opposed to : 28. Dimensional analysis of physical types Provisional number : E73 Summary: Extend the VHDL type model to support the dimensional analysis of physical quantities DESCRIPTION OF REQUIREMENT: It should be possible to write expressions involving physical quantities without having to overload the standard arithmetic operators. For example, it should be possible to multiply a variable of `type' voltage by one of `type' current and assign the result to something of `type' power without having to define an overloaded multiplication operator. This requirement re-states two requirements from the 1076 requirements ballot. Specifically E62 by D. Rodriguez and D. Rouqier and A18 by Alfred S. Gilman. SUGGESTED STRATEGIES: All physical quantities or units of measurement have dimensions defined in terms of seven basic physical units (metre, kilogramme, second, ampere, kelvin, candela and mole). These units are termed the `SI' units and are defined by the standard ISO-1000. For example, the unit of power, the watt, can be defined: 2 -3 1 W = 1 kg m s (Kilogramme, metre squared, per second cubed) If, when any physical type is defined, the dimensions of the type (in terms of the 7 basic SI units, which are perhaps defined using some standard package) are also specified then any assignment operations in the language can be checked for dimensional equivalence. The dimension specification could be added to the declaration of a physical type, using some suitable syntactic convention for expressing the various numerators and demoninators. Some rules for arithmetic operations (such as those in 1076 requirement E62) would be required to define how dimensioned quantities are arithmetically combined. 29. Domain of application Provisional number : E74 Summary : Description of requirement : The mixed language to be specified in IEEE1076.1 should enable the user to perform not only electrical simulation of digital circuits, but also analog simulation of "truely" analog circuits. In the first case, the electrical (and timing) performances of a digital circuit (e.g. adder, register) may be checked, and simplified simulation techniques may be used. In the second case, the behavior of an analog circuit (e.g. operational amplifier) may be checked, and precise simulation my be necessary. Clearly both styles must be possible when using IEEE1076.1 VHDL 92 solution : Suggested strategy : Check that no language feature prevents from modeling truely analog circuits. Possible problems : - definition of (analog) time (variable time-step must be possible) ; - definition of "DC" analysis to be performed at time 0. Consistent with : Different from : Opposed to : 30. Several modeling techniques Provisional number : E75 Summary : Description of requirement : The mixed language to be specified in IEEE1076.1 should provide the user several modeling techniques for the analog parts. Modeling by equations has already been proposed (see requirement E12). This method is simple and, in some cases, necessary. But it is well known that it leads to a greater number of equations in the equation-set. Procedural description should also be provided. In this method, analog blocks are seen as controlling their branch currents as functions of the node voltages (the node voltages are iteratively proposed by the analog kernel when solving the equation set, until the branch currents returned by analog blocks statisfy KCL). The "equation" method must be maintained and specified, because it is the only applicable method in some cases, but the "procedural" method must be added, because it will enable faster simulations. VHDL 92 solution : Suggested strategy : Study and specify the "analog procedural model" : - semantics (sequence of computation, with node voltages being read as input parameters, and branch current being returned as results) ; - instants at which the analog procedural model will be called by the analog "kernel" ; - syntax (could re-use most of the syntax of the digital process) ; Consistent with : Different from : Opposed to : 31. Consistency check for excitations and results in different analogue simulators Provisional number : E76 Summary: Signal typing and comparison possibility would be needed to be sure that input and output signals of different type of analogue simulators are consistent. Description of the requirement: In analog design, variety of simulation tools must usually be used (high-level programming languages for system behavioural verification, linear ac simulators for frequency responses and time domain simulators for non-linear effects) and the main problem seems not be the actual simulation but being sure that what you have simulated is what you have in the schematics. Simulating small sub-blocks, either linear or non-linear, is possible by describing appropriate input signals by hand to that particular simulator, but verifying the correctness of the whole circuit cannot usually be done: you cannot be sure that connections between sub-blocks (especially between analog and digital parts) have the right polarity and so on. It seems obvious, that VHDL itself is useful only in very simplified behavioural time domain analysis of analog circuits. What I would consider very useful is that different architecture descriptions of VHDL could be used as links or source code to different analog simulators that may run parallel with digital VHDL simulation. VHDL itself would be used as a design framework which takes care that the types and waveforms of input and output signals remain consistent, no matter what simulator is used. Suggested strategies: Firstly, I'm sorry to confess that I have no practical experience of using VHDL, so these are mere guesses which may not be practical at all. The strong signal typing capability of VHDL could be used to distinguish which signals are clocks, which ac-inputs or outputs and which mere dc voltage or current references. VHDL would check that current reference type signal is described by dc type source IBIAS in Spice, for example. Due to different accuracies of simulators, perhaps a visual comparison would be best. The framework would show e.g. transient results of a behavioural model to be used in VHDL simulation and from a Spice simulation on same time scale, and the designer's job is to verify that they agree close enough. Thus VHDL could be used to write spesifications of the function and to test that specs are fullfilled. 32. Analogue Modelling Requirements in VHDL Provisional number : E77 Descripiton: The following items would be required to give adequate analogue support in VHDL. 1/ Differential Equation specification for physical units eg di/dt, dv/dt 2/ New standard physical type definitions to cover current and power units 3/ A standard set of functions for often-used analogue sources eg sine, cosine, voltage/current controlled sources 4/ New VHDL signal type definitions that can contain current, voltage and phase angle information. 5/ Overloading of standard operators to support real and imaginary numbers (ie to handle phase-angle summations) Summary: By inventing some functions and new types many analogue issues can be addressed in the current 1076 standard. The most important issue is that their should be agreement on the names and definitions so that everyone adopts them. 33. Mixed entities required Provisional number : E78 Summary : Description of requirement : When using 1076.1, it should be possible to describe and simulate mixed (analog plus digital) circuits, circuits having digital I/Os (e.g. bits or bit-vectors, whether input, output or three-state) and analog I/Os (e.g. analog input or analog output). Thus it should be possible to declare an entity as having, at the same time, (digital) PORTS and (analog) PINS (and possibly GENERICS and PARAMETERS). VHDL 92 solution : Suggested strategy : Consistent with : Different from : Opposed to : 34. Implementation issues Provisional number : E79 Summary : Description of requirement : When defining 1076.1, attention should be paid to what is (easily ?) implemented and what is impossible (or nearly impossible) to implement. This should be done with the cooperation of people having an experience in the implementation of mixed simulators. Example of feasible things : - model an analog black box by a set of equations - model an analog black box by a procedural model - read a digital signal and use it in the analog behavior (with visibilty rules) - read an analog voltage and use it in the digital behavior (with visibilty rules) Examples of things which should be forbidden (by the syntax) - overwrite a digital signal from within an analog black box - overwrite an analog voltage from within a process - turn a voltage-source into a current-source and vice-versa VHDL 92 solution : Suggested strategy : Consistent with : Different from : Opposed to : 35. Single Timing Semantic Provisional number : A176 Description: Any extensions to the semantic timing model of VHDL should be incorporated into the existing timing model of the 92 standard or should handle the model used in the 92 standard. In particular, the evaluation of continuous-time models should be integrated with the evaluation of event-driven models into a single "simulation cycle" mechanism. 36. Pass Through of Analog Values Provisional number : A177 Description: The transferal of analog values through a communication channel which passes through a mixed component which contains digital elements but does not involve mixed digital/analog operations on those values should not require a conversion to the digital domain. 37. Fully Intermixed Designs Provisional number : A178 Description: Any extended language should allow the intermixing of any runtime statements, structural elements, or declarative statements within any of the structural blocks of the language. There should be no distinction between analog blocks/components/entities and digital blocks/components/entities. Consider the following case: Mixed Component --------------- +----------------->Mixed Interface-----------------+ | Digital Behavior | | | | Analog Component Analog Component | | ---------------- ---------------- | +-- Analog Source Analog Reader <----+ The analog reader should see the exact value generated by the analog source. 38. Specification of Initial Analog Conditions Provisional number : A179 Summary: The initialization of a VHDL model must be extended from the current procedural notation to something that allows the inclusion of initial analog characteristics. DESCRIPTION OF PROBLEM: A method for specifying the initial (time-zero) conditions of analog models must be provided. Examples of possible initial conditions are the charge on a capacitor, the flux of an inductor. More generally, an initial condition can be some voltage across or some current though a branch. If an initial condition is not specified, the simulator will use the value calculated from the DC solution of the circuit as the value for time-zero at a branch when transient analysis is performed. VHDL 87 SOLUTION: None 39. Specification of Non-conserved analog systems Provisional number : A180 Summary: It should be possible to specify non-conserved analog systems | in VHDL. This would extend the applicability of VHDL to | incude control system design. | DESCRIPTION OF PROBLEM: It should be possible to specify a non-conserved analog system to VHDL. A non-conserved (e.g. control) system use signal flow semantics to interconnect functional blocks. In other words, the signals form a directed graph of functional blocks. A functional block implements some function on the input signal(s), relating them to the output signal(s). VHDL 87 SOLUTION: None The following additional requirements were presented at VHDL-Forum ================================================================== 40.VDHL must facilitate a top down design methodology for analog systems from very high levels of abstraction (e.g. H(s), Control Loops, etc.) down through their physical implementations. The must include the specification of S domain expressions and related transfer functions. 41.VHDL must support the simulation of Sampled Data Systems and other DSP applications. The must include the specification of Z domain expressions and related transfer functions. 42.VHDL must be able to model analog noise sources and allow them to be conditionally injected into the behavior of a model. 43.VHDL must be able to model an ideal analog delay. 44.VHDL must be able to model ideal voltage and current sources. 45.VHDL must allow the specification, from within a model, of the next time step the simulator is guaranteed to evaluate. 46. VHDL must support the following functions and operators: * an intergal operator which allows the specificating of an initial condition * power of operator (** in FORTRAN) * random number function * transfer function whose arguments are the coefficients of S or Z poly's